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Core silicon · architecture in development
DFX-G7PCIe Gen7 Smart Switch
PCIe 7.0 switching with an AI engine built in. DFX-G7 is being designed to read deep telemetry from its own ports and from the Smart Backplane sensor fabric, and to predict thermal risk, faults and congestion where the data is produced.
Conceptual illustration
Spec-level facts. Product figures to follow.
Values below come from the PCIe 7.0 specification. DFX-G7 lane and port counts, latency, power and package will be published at product disclosure.
Spec figures from PCI-SIG ↗
A switch that thinks about what it carries.
Every PCIe transaction in the server crosses the switch. DFX-G7 adds the board's physical sensors to that view and runs inference next to the datapath, so decisions take effect without waiting for a round trip to a management server.
Telemetry from two sources, one inference engine.
The fabric side gives DFX-G7 per-port bandwidth, queue depth, credit state, error counters and link-training events. The backplane side streams bay temperature, voltage, current, airflow and drive health over the confidential sensor fabric. The AI engine aligns both on one timeline and scores the system continuously.
- Feature extraction in hardware. Rates, deltas and windowed statistics computed at line rate.
- Compact on-switch models. Risk scoring for thermal, fault and congestion, with confidence.
- Policy-bound actions. Operators decide what the switch may do on its own and what goes to DCIM.
Three predictions. Each with an action.
These are the core AI functions DFX-G7 is being designed to run, each tied to a specific operational response.
Predictive thermal control
Correlates bay temperatures and airflow from the backplane with traffic load on each port. When a hotspot is forecast, the switch can shift traffic away and request more cooling before devices throttle.
- Signals
- Bay temp, fan RPM, power, port utilization
- Predicts
- Time until thermal threshold per bay
- Acts
- Traffic shaping, fan-curve request, DCIM alert
Link and device fault prediction
Learns the normal error and latency signature of each link and device. Clustering correctable errors, rising retrains or drifting latency raise the risk score long before an uncorrectable error.
- Signals
- AER errors, retrains, latency, SMART, voltage
- Predicts
- Failure risk per link, slot and drive
- Acts
- Isolate port, drain device, open a work order
Intelligent load balancing
Forecasts congestion from queue growth and per-port demand, then reweights traffic classes and suggests placement, taking thermal headroom into account as well as bandwidth.
- Signals
- Queue depth, credits, bandwidth, thermal headroom
- Predicts
- Congestion onset per port and per job class
- Acts
- QoS reweighting, placement hints to schedulers
See what the fabric sees.
Select a link or a device to see the per-port telemetry the AI engine works from.
Bandwidth and latency
Per-port utilization and latency distributions, not only averages.
Queues and congestion
Queue depth, credit starvation and head-of-line blocking signals.
Errors and link state
Correctable and uncorrectable errors, retraining events and LTSSM transitions.
Backplane sensors
Bay temperature, power and airflow received over the sensor fabric.
From counters to decisions, on chip.
A programmable pipeline turns raw signals into actions. Operators define the policies the switch may execute.
Port counters, queues, errors, link state, backplane sensor frames.
Time-stamp and join fabric and physical signals per device.
Windowed rates, deltas, distributions, correlations.
Compact models score thermal, fault and congestion risk.
Policy engine weighs risk against operator guardrails.
Reweight QoS, isolate a port, alert and feed DCIM.
PCIe Gen7 at 128 GT/s
Full PCIe 7.0 signaling with PAM4 and flit-mode operation.
Configurable connectivity
Port bifurcation and flexible upstream and downstream assignment.
Low-latency switching
A datapath tuned for latency-sensitive GPU and accelerator traffic.
Embedded AI engine
On-die or near-die inference for telemetry-driven thermal, fault and load decisions.
Backplane sensor interface
Secure ingest of Smart Backplane sensor-fabric data.
Traffic management and QoS
Traffic classes, virtual channels and arbitration the AI engine can tune.
Multi-host architecture
One switch partitioned across several root complexes.
Virtualization
SR-IOV-aware routing for composable device pools.
Secure management
Out-of-band management, attested firmware and secure update.
AI data centers first. Every PCIe system next.
Intelligence at the heart of the PCIe fabric.
Architecture briefings are available under NDA to system architects at hyperscalers, OEMs and silicon partners.