CXL 3.0
Memory Disaggregation Backplane
A thermally zoned memory fabric designed to unlock large pooled DRAM deployments while keeping coherent interconnect performance stable under load. Sampling is planned for Q3 2026.
Technical Specifications
| Standard | CXL 3.0 (Coherent and non-coherent) |
| Signaling Speed | 64 GT/s PAM4 |
| Memory Pool | Up to 128 TiB disaggregated DRAM |
| Host Connections | Up to 16 host nodes |
| Thermal Design | Zoned DRAM cooling with controlled airflow boundaries |
| Operating Temp | -10°C to +80°C junction |
128TiB
Maximum pooled memory
16
Host nodes per backplane
Designed for memory pooling at production thermal loads
Memory fabric architects
Teams building coherent shared-memory designs that need predictable thermal behavior across large DRAM pools.
AI infrastructure builders
Programs that want disaggregated memory without letting thermal zoning become an operational blind spot.
HPC and research clusters
Environments pushing high utilization and large-memory workflows where conventional cooling layouts become unstable.
Key Features
Disaggregated Memory Pools
Enables large shared memory domains across multiple hosts without sacrificing thermal control.
Zoned Cooling Strategy
Separates high-density memory regions into controllable thermal zones for predictable behavior.
Fabric-Ready Connectivity
Built for coherent memory fabrics in dense AI and HPC cluster designs.
Adjacent systems for pooled-memory deployments
PCIe Gen6 Backplane
Use alongside the Gen6 fabric for mixed compute and memory expansion architectures.
View Product →ThermalOS Platform
Monitor pooled-memory thermals, rack zoning, and operational drift from a unified control plane.
View Product →LiquidReady Chassis
Bring liquid-ready infrastructure to memory-heavy cluster builds and dense rack zones.
View Product →