PCIe Gen6
Thermal-Aware Backplane
The world’s first thermally integrated PCIe Gen6 backplane. Designed from the substrate up to deliver 64 GT/s PAM4 signal integrity in operating environments up to 85°C.
Technical Specifications
| Standard | PCIe 6.0 (Backward compatible Gen 5/4) |
| Signaling Speed | 64 GT/s PAM4 per lane |
| Lane Count | Up to 256 lanes (configurable) |
| PCB Material | Megtron 8 with Thermal Core |
| Cooling | Passive conduction plus liquid channels |
| Operating Temp | -10°C to +85°C junction |
20dB
Max channel loss at 32GHz
85°C
Max signal integrity temperature
Built for teams pushing next-generation fabric density
AI server OEMs
Programs qualifying next-generation PCIe fabrics where thermal margin is now part of the channel design problem.
Hyperscale AI pods
Operators scaling dense training and inference clusters that need higher lane counts without hidden thermal reliability loss.
Advanced HPC platforms
Architectures moving to higher-speed interconnect backplanes under sustained utilization and elevated junction temperatures.
Key Features
Thermal-First Substrate
Co-designed thermal and electrical stack with embedded copper planes.
Liquid Channel Ready
Machined microfluidic channels for direct coolant flow within the PCB.
ThermalSense Integrated
Embedded sensor headers on every slot for real-time telemetry.
Build around the Gen6 thermal core
CXL 3.0 Backplane
Extend the same thermal-aware philosophy into coherent memory pooling and disaggregation.
View Product →ThermalSense Module
Instrument the Gen6 platform with predictive sensing and real-time thermal telemetry.
View Product →ThermalOS Platform
Tie the hardware into fleet-wide thermal visibility, alerting, and placement controls.
View Product →