PCIe Gen6 Thermal-Aware Smart Backplane
The only piece of silicon Datafabrix builds — and the only one the platform needs. A thermal-first, sensor-native PCIe Gen6 backplane delivering 64 GT/s PAM4 at sustained 85 °C junction, with an embedded ARM MCU running TinyML inference directly on the board.
Three things every other PCIe Gen6 backplane gets wrong.
A board can carry 64 GT/s signals. A board can run hot. A board can be passive. We refuse to accept any of those compromises.
Thermal & electrical co-designed
Most backplanes are routed for signal integrity, then handed to a thermal team to "make it survive". We design the substrate, copper thermal planes, and signal stack-up at the same time. 85 °C operation isn't a fault condition — it's the operating point.
Sensor-native
Junction temperature, lane-by-lane signal margin, per-slot power, thermal flux — all sampled at the board, at sub-second cadence, on every slot. The platform doesn't infer health from chassis sensors. It reads it from the substrate.
Intelligence on the board
An embedded ARM Cortex MCU runs TinyML inference directly on the backplane — anomaly scoring, lane-margin trending, thermal-flux prediction — without ever round-tripping to the host or the cloud.
Megtron 8 with embedded copper thermal planes.
At 32 GHz, dielectric choice and copper roughness dominate every error budget. We anchor the stack-up on Panasonic Megtron 8 — the lowest-loss high-speed material qualified for production PCIe Gen6 — and build copper thermal planes inside the stack to spread heat laterally before it ever reaches a device.
- Megtron 8 dielectric (Dk ≈ 3.0, Df ≈ 0.002) — 32 GHz channel loss budgeted to ≤ 20 dB end-to-end.
- VLP-3 ultra-low-roughness copper — minimizes conductor loss and improves long-channel reach.
- Embedded copper thermal planes co-designed with power & ground planes — lateral heat spreading without exotic cooling.
- Stripline / dual-stripline reference for all high-speed lanes — controlled-impedance, crosstalk-optimized.
- Symmetric layer construction minimizes warp under thermal cycling — qualified across −10 °C to +85 °C junction.
Exploded view — Megtron 8 dielectric, embedded copper thermal planes, signal & reference layers.
An ARM Cortex MCU. On the backplane. Always learning.
Inside the platform, intelligence flows from the silicon up. We place an ARM Cortex-M-class MCU directly on the backplane PCB. It owns the sensor fabric, runs calibration, and executes pre-trained TinyML models in the microsecond domain — entirely off the host path.
- On-board ARM Cortex MCU — owns sensor sampling, calibration, and on-board control loops.
- TinyML inference at the edge — sub-millisecond anomaly scoring on temperature, signal, and power telemetry.
- Lane-margin trend models — predict when a Gen6 lane is approaching its margin floor before the host even sees a CRC.
- Thermal-flux forecasting — short-horizon predictions feed local control loops without cloud round-trip.
- OTA-updatable model store — models evolve as ThermalOS learns across the fleet.
- Secure boot + signed firmware — enterprise-grade chain of trust on the sensor layer itself.
Embedded ARM Cortex MCU and surrounding ThermalSense sensor cluster.
Sensors on every slot.
ThermalSense is the sensor fabric built into the backplane. Each slot carries multiple sensing modalities, sampled together so the embedded MCU and ThermalOS can correlate thermal, electrical, and power events in one timeline.
Junction temperature
Multi-point on-board NTC + digital sensors. Per-slot junction-temperature estimation to ±1 °C, sampled at sub-second cadence.
Lane signal margin
Per-lane Gen6 PAM4 eye-margin telemetry exposed to the embedded MCU — no host CPU involvement required.
Per-slot power
High-side current sensing on every slot rail. Watt-accurate per-device power, with millisecond resolution for transient capture.
Thermal flux
Differential temperature sensors across copper thermal planes infer heat-flow direction and rate — not just hot-spots.
Voltage rail health
Per-rail ripple and droop monitoring. Catches PDN degradation before it becomes a Gen6 link failure.
Mechanical & seating
Per-slot insertion-detect, retention sensing, and humidity — surfaces the physical failures BMCs miss.
Hardware is the data plane.
Every module in the Datafabrix platform — Guardian, Thermal, Insight, StorageOS, Twin, Vision, Cloud — is only as accurate as the telemetry it receives. The Gen6 Thermal-Aware Smart Backplane is engineered to be that telemetry layer.
From substrate to dashboard, in one pipeline.
- Substrate sensors emit raw thermal, electrical, and power readings.
- Embedded MCU + TinyML calibrates, filters, and pre-scores at the board.
- ThermalOS streams calibrated telemetry into the AI Infrastructure Intelligence layer.
- Guardian, Thermal, StorageOS, Twin consume the same canonical signal — no impedance mismatch between layers.
- Cloud control plane closes the loop with policy actions back into the rack.
64 GT/s PAM4 — engineered for the long reach.
At Gen6, four-level PAM4 signaling collapses every error margin. Channel loss, crosstalk, jitter, and reference-plane integrity all have to land in budget — simultaneously.
| Signal-integrity budget | Datafabrix Gen6 Smart Backplane |
|---|---|
| Modulation | PAM4 (4-level, 32 GBd × 2) |
| Lane rate | 64 GT/s per lane (raw), 121 Gb/s effective per lane after FEC |
| End-to-end channel loss @ 32 GHz | ≤ 20 dB (slot-to-slot) |
| Insertion-loss deviation | ≤ 1.0 dB across temperature envelope |
| Return loss @ 32 GHz | ≤ −10 dB worst-case |
| NEXT / FEXT (worst-case) | ≥ 45 dB / ≥ 40 dB at Nyquist |
| Integrated random jitter (RJ) | ≤ 250 fs RMS contribution from substrate |
| Equalization assumption | Tx 3-tap FFE + Rx DFE; budget headroom preserved for retimer-less reach |
| Reach | Slot-to-slot, full-backplane (≥ 6 in. PCB) without retimers in baseline configuration |
PCIe Gen6 Thermal-Aware Smart Backplane — at a glance.
| Capability | Specification |
|---|---|
| Standard | PCIe 6.0 (backward compatible Gen 5 / 4) |
| Signaling | 64 GT/s PAM4 per lane |
| Max lanes | Up to 256 configurable |
| Substrate | Megtron 8 with embedded copper thermal planes |
| Cooling | Standard rack airflow — engineered copper thermal planes inside the PCB (no exotic cooling) |
| Channel loss | ≤ 20 dB at 32 GHz, end-to-end |
| Junction envelope | −10 °C to +85 °C sustained |
| Embedded processor | ARM Cortex-M-class MCU, secure boot, OTA-updatable firmware |
| On-board intelligence | TinyML inference — anomaly scoring, lane-margin trends, thermal-flux prediction |
| Telemetry | ThermalSense sensor fabric on every slot — junction temp, lane margin, power, thermal flux, PDN health, mechanical |
| Software interface | Native to ThermalOS & the Datafabrix Infrastructure Intelligence Platform |
| Compliance / safety | PCIe 6.0 CEM electrical compliance; UL recognized; CE / FCC class A targeted |
| Reliability target | MTBF > 600,000 h at 70 °C; symmetric layer construction qualified for thermal cycling |
| Target markets | AI server OEMs, hyperscale AI pods, advanced HPC platforms |
| Availability | Engineering samples 2026 · Production-ready 2027 |
From concept to engineering samples.
Stack-up locked, sensor topology defined
Megtron 8 stack-up, copper thermal-plane geometry, and ThermalSense sensor placement defined. Signal-integrity simulation closed against the 20 dB / 32 GHz budget.
EVT-1 fabrication & bring-up
First engineering samples fabricated. Embedded MCU brought up, ThermalSense fabric characterised end-to-end, signal compliance measured against simulation.
DVT with anchor partners
Selected AI server OEMs and hyperscalers integrate EVT boards into reference racks. ThermalOS pipeline closed against live substrate telemetry.
PVT & commercial readiness
Reliability, compliance, and qualification programs closed. Commercial production for design-win customers.